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Presentation on theme: "Asynchronous Sequential Logic"— Presentation transcript:

1 Asynchronous Sequential Logic
Chapter 9

2 9.1 Introduction Synchronous sequential circuits
Flip-flops share a single clockAsynchronous sequential circuits

3 Fig. 9.1Block diagram of an asynchronous sequential circuit

4 no clock pulsedifficult to designdelay elements: the propagation delaymust attain a stable state before the input is changed to a new valueDO NOT use asynchronous sequential circuits unless it is absolutely necessarye.g., in you exam

5 9-2. Analysis Procedure The procedure Determine all feedback loops
Assign Yi's (excitation variables), yi's (the secondary variables)Derive the Boolean functions of all Yi'sPlot each Y function in a mapConstruct the state tableCircle the stable states

6 Examples the excitation variables: Y1 and Y2 Fig. 9.2 Y1 = xy1+ x'y2
Example of an asynchronous sequential circuit

7 Maps and transition table
the y variables for the rowsthe external variable for the columnsCircle the stable statesY = yFig. 9.3Maps and transition table for the circuit of Fig. 9.2

8 The difference The total state
synchronous design: state transition happens only when the triggering edge of the clockasynchronous design: the internal state can change immediately after a change in the inputThe total statethe internal state + the input valuey: the present stateY: the next state

9 The state transition table

10 A flow tablea state transition table with its internal state being symbolized with lettersFig. 9-4(a) is called a primitive flow table because it has only one stable state in each rowFig. 9.4Example of flow tables

11 state assignment Þ derive the logic diagram
Fig. 9.5Derivation of a circuit specified by the flow table of Fig. 9.4(b)

12 Race conditions when two or more binary state variables change value
00 ® 1100 ® 10 ® 11 or 00 ® 01 ® 11a noncritical raceif they reach the same final stateotherwise, a critical state

13 Noncritical raceFig. 9.6Examples of non-critical races

14 Critical raceFig. 9.7Examples of critical races

15 Races may be avoided A cycle
race-free assignment: only one state can change at any one timeinsert intermediate unstable states with a unique state-variable changeA cyclea unique sequence of unstable states

16 A cycle a unique sequence of unstable states Fig. 9.8
Examples of cycles

17 Stability Considerations
a square waveform generator?Fig. 9.9Example of an unstable circuit

18 9-3 Circuits with Latches
Asynchronous sequential circuitswere know and used before synchronous designthe use of SR latches in asynchronous circuits produces a more orderly patternreduce the circuit complexity

19 SR latch - two cross-coupled NOR gates
Fig. 9.10SR latch with NOR gates

20 Y = ((S+y)'+R)' = (S+y)R' = SR'+R'y the state transition table
an unpredictable result when SR: 11 ® 00SR = 0 in operationSR' + SR = S(R'+R) = SÞ Y = S + R'y when SR = 0two cross-coupled NAND gateS'R' = 0Y = (S(Ry)')' = S'+ Ry when S'R' = 0S'R' latch

21 Fig. 9.11SR latch with NAND gates

22 Analysis exampleFig. 9.12Examples of a circuit with SR latch

23 Label each latch output with Yi and its external feedback path with yi
Derive the Boolean functions for the Si and RiS1 = x1y2R1 = x'1x'2S2 = x1x2R2 = x'2y1Check whether SR=0 for each NOR latch or whether S'R'=0 for each NAND latchS1R1 = x1y2x'1x'2 = 0S2R2 = x1x2x'2y1 = 0

24 Construct the state transition table Circle all stable states
Evaluate Y = S +R'y for each NOR latch or Y = S' + Ry for each NAND latchY1 = x1y2 + (x1+x2)y1 = x1y2+x1y1+x2y1Y2 = x1x2 + (x2+y'1)y2 = x1x2+x2y2+y'1y2Construct the state transition tableCircle all stable statesRace example:Let initial state isy1y2x1x2=1101input x2 is changed to 0if Y1 change to 0 before Y2then y1y2x1x2=0100instead of 0000Fig. 9.13Transition table for the circuit of Fig. 9.12

25  Analysis procedure:

26  Latch Excitation Table
 For SR latch:

27 Implementation Example
Determine the Boolean functions for the S and R inputs of each latchGiven a transition table From maps: the simplified Boolean functions areNOR latchNAND latch

28 Fig. 9.14Derivation of a latch circuit from a transition table

29  General Procedure for Implementing a Circuit with SR Latches
derive a pair of maps for Si and Riderive the simplified Boolean functions for each Si and RiDO NOT make Si and Ri equal to 1 in the same minterm squaredraw the logic diagramfor NAND latches, use the complemented values of those Si and Ri

30 Debounce circuitremove the series of pulses that result form a contact bounce and produce a single smooth transition of the binary signalTTL: input = logic-1 when openFig. 9.15Debounce circuit

31 9-4 Design Procedure Design specifications a gated latch
two inputs, G (gate) and D (data)one output, QG = 1: Q follows DG = 0 : Q remains unchanged

32 All the total states combinations of the inputs and internal states
simultaneous transitions of two input variables are not allowed

33 Primitive flow tabledash marks in each row that differs in two or more variables from the input variables associated with the stable statedon't care condition for the next state and outputFig. 9.16Primitive flow table

34 Reduction of the primitive flow table
two or more rows in the primitive flow table can be merged if there are non-conflicting states and outputs in each of the columns

35 Fig. 9.17Reduction of the primitive flow table

36 Transition table and logic diagram
State assignmentdiscussed in details in Sec. 9-6a:0, b:1Fig. 9.18Transition table and output map for gated latch

37 the outputlogic diagramFig. 9.19Gated-latch logic diagram

38 SR latch implementation
Fig. 9.20Circuit with SR latch

39 Assign outputs to unstable states
the unstable states have unspecified output valuesno momentary false outputs occur when the circuit switches between stable states0®0: 01 ® 1: 10 ® 1, 1 ® 0: -Fig. 9.21Assigning output values to unstable states

40 The procedure for making the assignment to outputs associated with unstable states can be summarized follows:

41 Summary a primitive flow table state reduction state assignment
output assignmentSimplify the Boolean functions of the excitation and output variables and draw the logic diagram

42 9-5 Reduction of State and Flow Table
Equivalent statesfor each input, two states give exactly the same output and go to the same next states or to equivalent next states

43 (a,b) are equivalent if (c,d) are equivalent
(a,b) imply (c,d)(c,d) imply (a,b)both pairs are equivalent

44 Implication Tablethe checking of each pair of states for possible equivalence

45 Fig. 9.22Implication table

46 the equivalent states the reduced states the state table
(a,b), (d,e), (d,g), (e,g)the reduced states(a,b), (c), (d,e,g), (f)the state table

47 Merging of the flow table
consider the don't-care conditionscombinations of inputs or input sequences may never occurtwo incompletely specified states that can be combined are said to be compatiblefor each possible input they have the same output whenever specified and their next states are compatible whenever they are specifieddetermine all compatible pairsfind the maximal compatiblesfind a minimal closed covering

48 Compatible pairs Fig. 9.23 Flow and implication tables
(a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f)Fig. 9.23Flow and implication tables

49 Maximal compatiblesa group of compatibles that contains all the possible combinations of compatible statesmerger diagramFig. 9.24Merger diagram

50 an isolated dot: a state that is not compatible to any other state
a line: a compatible paira triangle: a compatible with three statesan n-state compatible: an n-sided polygon with all its diagonals connectedFig. 9.24Merger diagram

51 Closed covering condition
cover all the statesclosedno implied states or the implied states are included within the set(a,c,d) (b,e,f)no implied statesanother example

52 Fig. 9.25Choosing a set of compatibles

53 (a,b) (c,d,e) (a,d) (b,c) (c,d,e) cover all the states but not closed
(b,c) are implied but not included(a,d) (b,c) (c,d,e)closedimplied states: (b,c) (d,e) (a,d)the same state can be repeated more than once

54 9-6 Race-Free State Assignment
To avoid critical racesonly one variable changes at any given timeThree-row flow-table exampleflow-table and transition diagram exampleFig. 9.26Three-row flow-table example

55 an extra row is addedno stable state in row dFig. 9.27Flow-table with an extra row

56 Transition TableFig. 9.28Flow-table with an extra row

57 Four-row flow-table example
flow-table and transition diagramFig. 9.29Four-row flow-table example

58 add extra rowsFig. 9.30Choosing extra rows for the flow table

59 the modified flow table
Fig. 9.31State assignment to modified flow table

60 Multiple-row method less efficient
multiple equivalent states for each stateFig. 9.32Multiple-row assignment

61 9-7 Hazards Unwanted switching transients at the output
different paths exhibit different propagation delaystemporary false-output value in combinational circuitsmay result in a transition to a wrong stable state in asynchronous sequential circuits

62 Hazards in combinational circuits
examplesFig. 9.33Circuits with hazards

63 static 1-hazard (sum of products)
the removal of static 1-hazard guarantees that no static 0-hazards or dynamic hazardsFig. 9.34Types of hazards

64 The remedy static 0-hazard (product of sum)
Y = (x1+x2')(x2+x3)The remedythe circuit moves from one product term to anotheradditional redundant gateFig. 9.35Maps illustrating a hazard and its removal

65 Hazard-free circuitFig. 9.36Hazard-free circuit

66 Hazards in sequential circuits
in general, no problem for synchronous designan asynchronous exampleFig. 9.37Hazard in a asynchronous sequential circuit

67 Implementation with SR latches
111 ® 110111 ® 010Implementation with SR latchesa momentary 0 signal at the S or R inputs of NOR latch has no effecta momentary 1 signal at the S or R inputs of NAND latch has no effect

68 Implementation with SR latches
Fig. 9.38Latch implementation

69 Implementation with SR latches
 For NAND SR latch:

70 Essential Hazards asynchronous sequential circuits
unequal delays along two or more paths that originate from the same inputcannot be corrected by adding redundant gatesthe delay of feedback loops > delays of other signals that originate from the input terminals

71 9.8 Design Example Summary of design procedure State the design spec.
Derive the primitive flow tableReduce the flow table by merging the rowsRace-free state assignmentObtain the transition table and output mapObtain the logic diagram using SR latches

72 Design Specification

73 Primitive Flow tableFig. 9.39Primitive flow table

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